Power Device Packages Having Thermal Electric Modules Using Peltier Effect and Methods of Fabricating the Same

ABSTRACT

Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the benefit of Korean Patent Application No.10-2008-0029311, filed on Mar. 28, 2008, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in itsentirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power device packages and methods offabricating the same, and more particularly, to power device packages,each of which includes a thermal electric module using the Peltiereffect and thus can improve operational reliability by rapidlydissipating heat generated during operation to the outside, and methodsof fabricating the power device packages.

2. Description of the Related Art

As the power electronic industry develops power devices, such as powertransistors, insulated-gate bipolar transistors (IGBTs), MOStransistors, silicon-controlled rectifiers (SCRs), power rectifiers,servo drivers, power regulators, inverters, and converters, demands forlighter and smaller power products with improved performance areincreasing. To meet these demands, research is being actively conductedon smart power modules or intelligent power modules, which can integratenot only various power semiconductor chips into a single package butalso include control semiconductor chips, such as integrated circuitchips, for controlling the power semiconductor chips.

Conventional power device packages have been fabricated by mounting aplurality of semiconductor chips on a substrate. For example, U.S. Pat.No. 5,703,399 assigned to Mitsubishi discloses a power device package inwhich power semiconductor chips and control semiconductor chips mountedon one lead frame are molded into one package. Typically, since powerdevice packages generate heat during operation, it is important torapidly dissipate the heat to the outside for reliable operation. Sincethe generated heat is generally discharged to the outside through asubstrate, when a substrate, such as a ceramic substrate, having a lowheat transfer coefficient, is used, there is a limitation in improvingheat transfer characteristics.

BRIEF SUMMARY OF THE INVENTION

The present invention provides power device packages that includethermal electric modules using the Peltier effect and thus can improveoperational reliability by rapidly dissipating heat generated duringoperation to the outside.

The present invention also provides methods of fabricating power devicepackages that include thermal electric modules using the Peltier effectand thus can improve operational reliability by rapidly dissipating heatgenerated during operation to the outside.

According to an aspect of the present invention, there is provided apower device package including: a thermal electric module having a firstsurface and a second surface opposite each other, and a plurality ofn-type impurity elements and a plurality of p-type impurity elementsalternately and electrically connected to each other in series; a leadframe attached to the first surface of the thermal electric module by anadhesive member; one or more power semiconductor chips disposed on andelectrically connected to the lead frame; one or more controlsemiconductor chips disposed on and electrically connected to the leadframe to control at least one the power semiconductor chip; and asealing member sealing the thermal electric module, the one or morepower semiconductor chips, the one or more control semiconductor chips,and at least a portion of the lead frame so as to expose the secondsurface of the thermal electric module.

In an embodiment of the present invention, the thermal electric modulemay include: an impurity element array portion having the n-typeimpurity elements and the p-type impurity elements alternately arrangedwith respect to each other; a plurality of conductive membersrespectively formed on and below the impurity element array portion andelectrically connecting the n-type impurity elements and the p-typeimpurity elements in series; a power wiring electrically connected to aportion of the conductive members so as to supply DC (direct current)power to the impurity element array portion from the outside; and aplurality of insulating members respectively attached on and below theconductive members opposite to the impurity element array portion.

In an embodiment of the present invention, the impurity element arrayportion comprises a semiconductor substrate, the n-type impurityelements are n-type impurity regions formed by doping or ion implantingn-type impurities in the semiconductor substrate, and the p-typeimpurity elements are p-type impurity regions formed by doping or ionimplanting p-type impurities in the semiconductor substrate.

In an embodiment of the present invention, the conductive members mayinclude aluminum, an aluminum alloy, copper, a copper alloy, nickel, anickel alloy or a combination thereof. The power wiring may beelectrically connected to the lead frame so as to supply DC power to theimpurity element array portion.

In an embodiment of the present invention, the n-type impuritiesincluded in the n-type impurity elements include one or more selectedfrom the group consisting of N, P, As, Sb, Bi, S, Se, Te, and Po, andthe p-type impurities included in the p-type impurity elements includeone or more selected from the group consisting of B, Al, Ga, In, Tl, Zn,Cd, and Hg.

In an embodiment of the present invention, one or both of the powersemiconductor chips and the control semiconductor chips may be mountedto be electrically connected to the lead frame in the form of flip chipsor are electrically connected to the lead frame by using wires or solderballs. Each wire may include aluminum (Al) or gold (Au).

In an embodiment of the present invention, the power semiconductor chipsmay include power metal oxide semiconductor field effect transistors(MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolartransistors (IGBTs), diodes, or combinations thereof.

In an embodiment of the present invention, the sealing member mayinclude an epoxy molding compound (EMC), a polyimide, a silicone, asilicone rubber, or a combination thereof.

In an embodiment of the present invention, the power device package mayfurther include a heat sink attached to the second surface of thethermal electric module and dissipating heat. The heat sink may includealuminum, an aluminum alloy, copper, a copper alloy, Al₂O₃, BeO, AlN,SiN, an epoxy-based resin, or a combination thereof.

In an embodiment of the present invention, the lead frame adhesivemember may include an elastomer or an epoxy.

According to another aspect of the present invention, there is provideda power device package including: a thermal electric module having afirst surface and a second surface opposite each other, and a pluralityof n-type impurity elements and a plurality of p-type impurity elementsalternately and electrically connected to each other in series; a wiringpattern disposed on the first surface; a lead frame attached to thefirst surface of the thermal electric module by a conductive adhesivemember and electrically connected to the wiring pattern; one or morepower semiconductor chips disposed on and electrically connected to thewiring pattern; one or more control semiconductor chips disposed on andelectrically connected to the lead frame, the wiring pattern, or both tocontrol at least one power semiconductor chip; and a sealing membersealing the thermal electric module, the one or more power semiconductorchips, the one or more control semiconductor chips, and at least aportion of the lead frame so as to expose the second surface of thethermal electric module.

In an embodiment of the present invention, the wiring pattern mayinclude aluminum, an aluminum alloy, copper, a copper alloy, or acombination thereof. The wiring pattern may further include nickel,gold, or an alloy thereof. The conductive adhesive member may include asolder, a solder paste, a silver (Ag) paste, or a combination thereof.

In an embodiment of the present invention, one or both of the powersemiconductor chips and the control semiconductor chips may be mountedto be electrically connected to the wiring pattern or the lead frame inthe form of flip chips or be electrically connected to the wiringpattern or the lead frame by using wires or solder balls. Each wire mayinclude aluminum (Al) or gold (Au).

According to another aspect of the present invention, there is provideda method of fabricating a power device package, the method including:assembling a lead frame and a first surface of a thermal electric moduletogether using an adhesive member, the thermal electric module having asecond surface opposite to the first surface, a plurality of n-typeimpurity elements, and a plurality of p-type impurity elements, then-type impurity elements and the p-type impurity elements beingalternately and electrically connected to each other in series; mountingone or more power semiconductor chips and one or more controlsemiconductor chips on the lead frame; electrically connecting at leastone power semiconductor chip and at least one control semiconductor chipto the lead frame; and sealing the thermal electric module, the one ormore power semiconductor chips, the one or more control semiconductorchips, and a portion of the lead frame with a sealing member so as toexpose the second surface of the thermal electric module.

According to another aspect of the present invention, there is provideda method of fabricating a power device package, the method including:preparing a thermal electric module having a first surface and a secondsurface opposite to each other, and a plurality of n-type impurityelements and a plurality of p-type impurity elements alternately andelectrically connected to each other in series; attaching a lead frameonto the first surface of the thermal electric module using a lead frameadhesive member; mounting one or more power semiconductor chips and oneor more control semiconductor chips on the lead frame; electricallyconnecting the power semiconductor chips and the control semiconductorchips respectively to the lead frame; and sealing the thermal electricmodule, the power semiconductor chips, the control semiconductor chipsand a portion of the lead frame by using a sealing member so as toexpose the second surface of the thermal electric module.

In an embodiment of the present invention, the attaching of the leadframe further may include electrically connecting the thermal electricmodule and the lead frame.

In an embodiment of the present invention, after the sealing of thesubstrate, the power semiconductor chips, and the portion of the leadframe, the method further includes: performing trimming to leave onlyexternal leads exposed to the outside of the sealing member among otherleads of the lead frame; and performing forming to bend the externalleads.

According to another aspect of the present invention, there is provideda method of fabricating a power device package, the method including:forming a wiring pattern on a first surface of a thermal electricmodule, the thermal electric module having a second surface opposite tothe first surface, a plurality of n-type impurity elements, and aplurality of p-type impurity elements, the n-type impurity elements andthe p-type impurity elements being alternately and electricallyconnected to each other in series; mounting one or more powersemiconductor chips on the thermal electric module so as to electricallyconnect to the wiring pattern; assembling a lead frame and the firstsurface of the thermal electric module together using a conductiveadhesive member so that the lead frame and the wiring pattern areelectrically connected; and sealing the thermal electric module, thepower semiconductor chips, the control semiconductor chips and a portionof the lead frame with a sealing member so as to expose the secondsurface of the thermal electric module.

According to another aspect of the present invention, there is provideda method of fabricating a power device package, the method including:preparing a thermal electric module having a first surface on which awiring pattern is formed and a second surface opposite to the firstsurface, and a plurality of n-type impurity elements and a plurality ofp-type impurity elements alternately and electrically connected to eachother in series; attaching a lead frame to the first surface of thethermal electric module using a lead frame adhesive member; mounting oneor more power semiconductor chips and one or more control semiconductorchips on the lead frame; electrically connecting at least one powersemiconductor chip and at least one control semiconductor chiprespectively to the lead frame; and sealing the thermal electric module,one or more the power semiconductor chips, the one or more controlsemiconductor chips and a portion of the lead frame by using a sealingmember so as to expose the second surface of the thermal electricmodule.

In an embodiment of the present invention, the mounting the powersemiconductor chips on the wiring pattern to be electrically connectedfurther includes mounting one or more control semiconductor chips on thewiring pattern so as to be electrically connected to the wiring pattern.

In an embodiment of the present invention, the action of attaching thelead frame further includes electrically connecting the thermal electricmodule and the lead frame.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail exemplary embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a schematic cross-sectional view of a power device packageaccording to an embodiment of the present invention;

FIG. 2 is a view for describing an operational principle of a thermalelectric module included in the power device package of FIG. 1;

FIG. 3A is a schematic perspective view of an example of the thermalelectric module included in the power device package of FIG. 1;

FIG. 3B is a schematic cross-sectional view of another example of thethermal electric module included in the power device package of FIG. 1;

FIGS. 4A through 4F are schematic cross-sectional views illustrating amethod of fabricating the power device package of FIG. 1 according to anembodiment of the present invention;

FIG. 5 is a schematic cross-sectional view of a power device packageaccording to another embodiment of the present invention; and

FIGS. 6A through 6D are schematic cross-sectional views illustrating amethod of fabricating the power device package of FIG. 5 according toanother embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to example embodiments, examples ofwhich are illustrated in the accompanying drawings. However, exampleembodiments are not limited to the embodiments illustrated hereinafter,and the embodiments herein are rather introduced to provide easy andcomplete understanding of the scope and spirit of example embodiments.In the drawings, the thicknesses of layers and regions are exaggeratedfor clarity.

It will be understood that when an element, such as a layer, a region,or a substrate, is referred to as being “on”, “connected to” or “coupledto” another element, it may be directly on, connected or coupled to theother element or intervening elements may be present. In contrast, whenan element is referred to as being “directly on,” “directly connectedto” or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like reference numerals refer tolike elements throughout. As used herein, the term “and/or” includes anyand all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of example embodiments.

Spatially relative terms, such as “above,” “upper,” “beneath,” “below,”“lower,” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “above” may encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofexample embodiments (and intermediate structures). As such, variationsfrom the shapes of the illustrations as a result, for example, ofmanufacturing techniques and/or tolerances, are to be expected. Thus,example embodiments should not be construed as limited to the particularshapes of regions illustrated herein but may be to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may, typically, have roundedor curved features and/or a gradient of implant concentration at itsedges rather than a binary change from implanted to non-implantedregion. Likewise, a buried region formed by implantation may result insome implantation in the region between the buried region and thesurface through which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes maynot be intended to illustrate the actual shape of a region of a deviceand are not intended to limit the scope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a schematic cross-sectional view of a power device package 10according to an embodiment of the present invention.

Referring to FIG. 1, the power device package 10 includes a thermalelectric module 100 and a lead frame 120, one or more powersemiconductor chips 140 and 142, one or more control semiconductor chips144 and 146, and a sealing member 160. The thermal electric module 100includes a first surface 112 and a second surface 114 opposite eachother, and a plurality of n-type impurity elements 101 (shown in FIG. 2)and a plurality of p-type impurity elements 102 (shown in FIG. 2)alternately and electrically connected to each other in series.Components and an operational principle of the thermal electric module100 will now be described in detail. The lead frame 120 is attached tothe first surface 112 of the thermal electric module 100 by using a leadframe adhesive member 110. The one or more power semiconductor chips 140and 142 are mounted (i.e., disposed) on the lead frame 120 and areelectrically connected to one another. The one or more controlsemiconductor chips 144 and 146 are mounted (i.e., disposed) on the leadframe 120 and are electrically connected to one another to control oneor more of the power semiconductor chips 140 and 142. The sealing member160 seals the thermal electric module 100, the power semiconductor chips140 and 142, the control semiconductor chips 144 and 146, and at least aportion of the lead frame 120 so as to expose the second surface 114 ofthe thermal electric module 100. The power device package 10 may furtherinclude a heat sink 170 attached to the second surface 114 of thethermal electric module 100; heat sink 170 is used to dissipate heat.

FIG. 2 is a view for describing an operational principle of a thermalelectric module included in the power device package of FIG. 1.

Referring to FIG. 2, the thermal electric module 100 includes the n-typeimpurity element 101 and the p-type impurity element 102 which areelectrically connected to each other. In detail, an upper portion of then-type impurity element 101 and an upper portion of the p-type impurityelement 102 are electrically connected to each other by an upperconductive member 105. A lower portion of the n-type impurity element101 and a lower portion of the p-type impurity element 102 are spacedapart from each other and connected to an external power source 190through a lower conductive member 106. Insulating members 107 and 108,such as ceramic materials, are respectively attached on and below theupper conductive member 105 and the lower conductive member 106, whichare opposite each other.

The n-type impurity element 101 includes a medium, such as silicon orsilicon-germanium, with n-type impurities. The n-type impurities includeone or more selected from the group consisting of nitrogen (N),phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulphur (S),selenium (Se), tellurium (Te), and polonium (Po). The p-type impurityelement 102 includes a medium, such as silicon or silicon-germanium,with p-type impurities. The p-type impurities include one or moreselected from the group consisting of boron (B), aluminum (Al), gallium(Ga), indium (In), thallium (Tl), zinc (Zn), cadmium (Cd), andhydrargyrum (Hg).

When direct current (DC) electrical power is applied to the n-typeimpurity element 101 and the p-type impurity element 102 by the externalpower source 190, electrons move in a direction opposite to the currentflow direction, and holes move in a same direction as the current flowdirection. Accordingly, the main carriers in the n-type impurity element101 are the electrons 1 which move in a downward direction opposite tothe current flow direction, that is, from a region adjacent to the upperconductive member 105 to a region adjacent to the lower conductivemember 106. On the other hand, the main carriers in the p-type impurityelement 102 are the holes 2 which move in a same downward direction asthe current flow direction, that is, from a region adjacent to the upperconductive member 105 to a region adjacent to the lower conductivemember 106. Consequently, both the electrons 1 and the holes 2 flow inthe same direction. The electrons 1 and the holes 2 moved by the DCcurrent become carriers for transferring heat through the external powersource 190, and the heat transfer direction is illustrated with arrowsin FIG. 2. As such, when current is applied across different types ofsolid matter or semiconductors, heating or heat absorption differentfrom Joule heat is generated, and this is called the Peltier effect.Typically, the Peltier effect denotes movement of heat generated due tocurrent flow when different materials, such as metals or semiconductors,are joined to each other to become a junction. Accordingly, in FIG. 2,the n-type impurity element 101 is joined to the upper conductive member105 and the lower conductive member 106 to become a junction, andseparately, the p-type impurity element 102 is also joined to the upperconductive member 105 and the lower conductive member 106 to becomeanother junction. Consequently, the upper conductive member 105 and thelower conductive member 106 respectively become a low-temperatureportion and a high-temperature portion by the heat transfer as describedabove.

The power semiconductor chips 140 and 142 and/or the controlsemiconductor chips 144 and 146 are mounted on the upper conductivemember 105 as illustrated in FIG. 1. The heat, generated due tooperation of the power semiconductor chips 140 and 142 and/or thecontrol semiconductor chips 144 and 146, moves toward the lowerconductive member 106 via the n-type impurity element 101 or the p-typeimpurity element 102 according to the aforementioned principle, and thenis dissipated to the outside.

FIG. 3A is a schematic perspective view of an example of the thermalelectric module 100 included in the power device package of FIG. 1.

Referring to FIG. 3A, the thermal electric module 100 includes animpurity element array unit 103, the upper and lower conductive members105 and 106, a power wiring 109, and the insulating members 107 and 108.The impurity element array unit 103 includes the n-type impurityelements 101 and the p-type impurity elements 102 alternately arrangedas described above with reference to FIG. 2. The upper and lowerconductive members 105 and 106 are respectively formed (i.e., disposed)on and below the impurity element array unit 103, as shown in FIG. 3A.The conductive members 105 and 106 electrically connect the n-typeimpurity elements 101 and the p-type impurity elements 102 in series.The upper and lower conductive members 105 and 106 may include aluminum,an aluminum alloy, copper, a copper alloy, nickel, or a nickel alloy, ora combination thereof. The power wiring 109 is connected to a portion ofthe conductive members 105 and 106 so as to apply DC current to theimpurity element array unit 103. To apply the DC current, the powerwiring 109 may be electrically connected to the lead frame 120 (seeFIG. 1) or to a separate external circuit. The insulating members 107and 108 are respectively attached to the upper and lower conductivemembers 105 and 106, which face each other across the impurity elementarray unit 103. According to the above structure, the DC current appliedthrough the power wiring 109 from the outside alternately passes throughthe n-type impurity elements 101 and the p-type impurity elements 102.Thus, heat is transferred from the upper conductive members 105 to thelower conductive members 106 by the Peltier effect described above withreference to FIG. 2, and consequently, the heat is dissipated to theoutside.

FIG. 3B is a schematic cross-sectional view of another example of thethermal electric module 100 a included in the power device package ofFIG. 1. For convenience and accuracy, repeated explanations ofoverlapped features will not be given.

Referring to FIG. 3B, the thermal electric module 100 a includes animpurity element array unit 103 a, conductive members 105 a and 106 a, apower wiring 109, and insulating members 107 a and 108 a. The thermalelectric module 100 a according to the current embodiment has thefollowing main features. The impurity element array unit 103 a comprisesa semiconductor substrate 104 a, such as a silicon substrate or asilicon-germanium substrate, a plurality of n-type impurity elements 101a disposed in substrate 104 a, and a plurality of p-type impurityelements 102 a disposed in substrate 104 a. The plurality of n-typeimpurity elements 101 a may comprise n-type impurity regions formed bydoping or ion implanting n-type impurities in the semiconductorsubstrate 104 a, and the plurality of p-type impurity elements 102 a maycomprise p-type impurity regions formed by doping or ion implantingp-type impurities in the semiconductor substrate 104 a. The conductivemembers 105 a and 106 a may comprise conductive patterns formed on then-type impurity elements 101 a and the p-type impurity elements 102 a,respectively. The insulating members 107 a and 108 a may comprise anoxide, a nitride, or the like, and may be formed by a layer formingmethod used in a conventional semiconductor manufacturing method.However, this is exemplary and the present invention is not limitedthereto. The arrangement of the n-type impurity elements 101 a and thep-type impurity elements 102 a and an electrical connection between then-type impurity elements 101 a and the p-type impurity elements 102 avia the conductive members 105 a and 106 a have been described withreference to FIG. 3A. That is, the n-type impurity elements 101 a andthe p-type impurity elements 102 a are electrically connected to eachother in series by the conductive members 105 a and 106 a, and DCcurrent is applied to the n-type and p-type impurity elements 101 a and102 a from an external power source by the power wiring 109 a, and thusheat transfer is realized by the Peltier effect as described above.

FIGS. 4A through 4F are schematic cross-sectional views illustrating amethod of fabricating the power device package 10 of FIG. 1 according toan embodiment of the present invention.

Referring to FIG. 4A, a thermal electric module 100 having a firstsurface 112 and a second surface 114 opposite each other is prepared.The thermal electric module 100 includes a plurality of n-type impurityelements and a plurality of p-type impurity elements alternately andelectrically connected to each other in series, and the operationalprinciple thereof has been described above with reference to FIG. 2 andits components are the same as those of embodiments described withreference to FIG. 3A or FIG. 3B. However, the materials are exemplaryand the present invention is not limited thereto. A lead frame adhesivemember 110 is formed on the first surface 112 of the thermal electricmodule 100 and may include an elastomer or an epoxy. The elastomerdenotes a polymer having good elasticity, and thus the elastomerstretches when an external force is applied to the elastomer and returnsto its original state when the external force is removed from theelastomer. The elastomer is called an elastic polymer. An elasticrubber, such as butadiene or styrene, or an elastic fiber, such asspandex, may be representative of an elastic polymer. The lead frameadhesive member 110 may be conductive or non-conductive. For example,the lead frame adhesive member 110 may be formed by plating, or maycomprise a conductive paste or a conductive tape. Also, the lead frameadhesive member 110 may comprise a solder, a metal epoxy, a metal paste,a resin-based epoxy, or an adhesive tape with high heat resistance. Forexample, the adhesive tape may comprise a well-known hightemperature-resistant tape such as a common glass tape, a silicone tape,a Teflon tape, a stainless foil tape, or a ceramic tape. Alternatively,the lead frame adhesive member 110 may be formed by combining theaforementioned materials. However, the forming of the lead frameadhesive member 110 and the materials thereof are exemplary and thepresent invention is not limited thereto.

Referring to FIG. 4B, a lead frame 120 is attached to the lead frameadhesive member 110 formed on the first surface 112 of the thermalelectric module 100 (that is, in general, the lead frame and the thermalelectric module are assembled together). In a later process, the powersemiconductor chips 140 and 142 are mounted on an end portion 120 a ofthe lead frame 120, which is directly attached to the lead frameadhesive member 110. On the other hand, in a later process, the controlsemiconductor chips 144 are mounted on another end portion 120 b of thelead frame 120, which is not directly attached to the lead frameadhesive member 110. The end portion 120 a of the lead frame 120 and theend portion 120 b of the lead frame 120 are electrically connected toeach other by a lead frame wiring 122. Alternatively, the lead frame 120may be integrally formed with the end portion 120 a and the end portion120 b, or may be separately formed to respectively include the endportion 120 a and the end portion 120 b.

Next, the thermal electric module 100 and the lead frame 120 areelectrically connected to each other. That is, the power wiring 109illustrated in FIG. 3A or FIG. 3B is electrically connected to the leadframe 120, so that electric power can be supplied to the thermalelectric module 100. In FIG. 4B, the power wiring 109 is connected tothe other end portion 120 b of the lead frame 120; however, this isexemplary, and the power wiring 109 may be connected to the end portion120 a of the lead frame 120. The electrical connection between the leadframe 120 and the power wiring 109 may be realized by using aconventional method, such as a soldering method. Although not shown inthe drawing, the power wiring 109 may be connected to an externalcircuit without being connected to the lead frame 120, so that power canbe supplied to the thermal electric module 100.

Referring to FIG. 4C, one or more power semiconductor chips 140 and 142are mounted on the lead frame 120. The power semiconductor chips 140 and142 may be attached to the lead frame 120 by using a chip adhesivemember 130. The chip adhesive member 130 may comprise the same materialas the aforementioned lead frame adhesive member 110. The powersemiconductor chips 140 and 142 may comprise power circuit chips forpower conversion or power control such as servo drivers, inverters,power regulators, or converters. For example, the power semiconductorchips 140 and 142 may include power metal oxide semiconductor fieldeffect transistors (MOSFETs), bipolar junction transistors (BJTs),insulated-gate bipolar transistors (IGBTs), diodes, or combinationsthereof. In other words, the power semiconductor chips 140 and 142 mayinclude any or all of the listed items. For example, two powersemiconductor chips 140 and 142 shown in FIG. 4C may comprise an IGBTand a diode, respectively. As such, the power device package 10 mayinclude six power semiconductor chip pairs, each such pair including oneIGBT and one diode. However, this is exemplary and the present inventionis not limited thereto.

One or more control semiconductor chips 144 and 146 (which will beelectrically connected so as to control the power semiconductor chips140 and 142) are mounted on the lead frame 120. The controlsemiconductor chips 144 and 146 may be generally mounted on the endportion 120 b of the lead frame 120, and also may be mounted on the endportion 120 a of the lead frame 120. The control semiconductor chips 144and 146 may comprise microprocessors, passive devices, such asresistors, inverters, or condensers, and/or active devices, such astransistors, etc. One power device package 10 may include a few to tensof control semiconductor chips 144 and 146. It may be appreciated thatthe type and number of the control semiconductor chips 144 and 146 canbe determined according to the type and number of the powersemiconductor chips 140 and 142.

Referring to FIG. 4D, the power semiconductor chips 140 and 142 and thelead frame 120 are electrically connected to each other. The powersemiconductor chips 140 and 142 may be electrically connected to thelead frame 120 in the form of flip chips, or may be electricallyconnected to the lead frame 120 by using wires or solder balls. In FIG.4D, the power semiconductor chip 140 is electrically connected to thelead frame 120 by using one or more wires 150, and the powersemiconductor chip 142 is electrically connected to the lead frame 120in the form of flip chips or by using a solder ball (not shown).However, this is exemplary and the present invention is not limitedthereto. Each wire 150 may include a metal such as aluminum (Al), analuminum alloy, gold (Au), or a gold alloy. Each wire 150 may beconnected to the power semiconductor chips 140 and to the lead frame 120by ball bonding, wedge bonding, or stitch bonding, all of which are wellknown in the art. For this electrical connection, each of the powersemiconductor chips 140 and 142 and the lead frame 120 may include aconnection portion such as a typical connection pad. It may beappreciated that only one or both types of the power semiconductor chip140 (which is electrically connected to the lead frame 120 by using thewire 150) and the power semiconductor chip 142 (which is electricallyconnected to the lead frame 120 in the form of flip chips or by usingthe solder ball) may be mounted in the power device package 10.

Similarly, the control semiconductor chips 144 and 146 and the leadframe 120 are electrically connected to each other. The controlsemiconductor chips 144 and 146 may be electrically connected to thelead frame 120 in the form of flip chips, or may be electricallyconnected to the lead frame 120 by using wires or solder balls. In FIG.4D, the control semiconductor chips 144 are electrically connected tothe lead frame 120 by using wires 150, and the control semiconductorchips 146 are electrically connected to the lead frame 120 in the formof flip chips or by using a solder ball (not shown). However, this isexemplary and the present invention is not limited thereto. The wire 152may include a metal such as aluminum (Al), an aluminum alloy, gold (Au),or a gold alloy. Each wire 152 may be connected to the controlsemiconductor chip 144 and to the lead frame 120 by ball bonding, wedgebonding, or stitch bonding, all of which are well known in the art. Forthis electrical connection, each of the control semiconductor chips 144and 146 and the lead frame 120 may include a connection portion such asa typical connection pad. It may be appreciated that only one or bothtypes of the control semiconductor chip 144 (which is electricallyconnected to the lead frame 120 by using the wire 152) and the controlsemiconductor chip 146 (which is electrically connected to the leadframe 120 in the form of a flip chip or by using solder balls) may bemounted in the power device package 10. Accordingly, the controlsemiconductor chips 144 and 146 are electrically connected to the powersemiconductor chips 140 and 142 through the lead frame 120, so that thecontrol semiconductor chips 144 and 146 can control the operations ofthe power semiconductor chips 140 and 142.

In addition to the method described above with reference to FIGS. 4Bthrough 4D, a method of attaching the lead frame 120 to the thermalelectric module 100 after mounting the power semiconductor chips 140 and142 and/or the control semiconductor chips 144 and 146 on the lead frame120 is included in the scope of the present invention.

Referring to FIG. 4E, the power device package 10 is encapsulated byusing a sealing member 160 by performing a typical transfer moldingprocess or a curing process. The sealing member 160 may seal the thermalelectric module 100, the power semiconductor chips 140 and 142, and thecontrol semiconductor chips 144 and 146, and may expose the secondsurface 114 of the thermal electric module 100. Also, the sealing member160 seals a portion of the lead frame 120, and external leads 120 c and120 d of the lead frame 120 which are exposed to the outside areelectrically connected to the outside of the power device package 10.The sealing member 160 may include an insulating resin, for example, anepoxy molding compound (EMC), a polyimide, a silicone, or a siliconerubber, or a combination thereof. It may be appreciated that the powerdevice package 10 may have various shapes depending on the shape of anexternal mold (not shown) in which the sealing member 160 is made.

Referring to FIG. 4F, trimming of the leads of lead frame 120 isperformed so that only the external leads 120 c and 120 d are leftexposed to the outside of the sealing member 160, and bending of theexternal leads 120 c and 120 d is performed, thereby completing thepower device package 10. As a result of the trimming, the trimmed leadsof lead frame 120 are encased by sealing member 160 and do not extendout from the package.

Referring to FIG. 1 again, the power device package 10 may furtherinclude a heat sink 170 attached to the exposed second surface 114 ofthe thermal electric module 100; the heat sink 170 is used to dissipateheat. The heat sink 170 may include a metal, a metal nitride, a ceramic,a resin, or a combination thereof For example, the heat sink 170 mayinclude aluminum, an aluminum alloy, copper, a copper alloy, an aluminumoxide (Al₂O₃), a beryllium oxide (BeO), an aluminum nitride (AIN), asilicon nitride (SiN), an epoxy-based resin, or a combination thereofThe heat sink 170 may have various dimensions and shapes in order tomore effectively dissipate heat. The heat sink 170 may be attached tothe thermal electric module 100 by using a solder, a metal epoxy, ametal paste, a resin-based epoxy, or an adhesive tape with high heatresistance. The adhesive tape may comprise a well-known hightemperature-resistant tape such as a glass tape, a silicone tape, aTeflon tape, a stainless foil tape, or a ceramic tape, or a tapeincluding an aluminum oxide, an aluminum nitride, a silicon oxide, or aberyllium oxide. The solder may include a metal such as lead (Pb),lead/tin (Pb/Sn), tin/silver (Sn/Ag), or lead/tin/silver (Pb/Sn/Ag).

FIG. 5 is a schematic cross-sectional view of a power device package 20according to another embodiment of the present invention. Forconvenience and accuracy, repeated explanations of overlapped featureswill not be given.

Referring to FIG. 5, the power device package 20 includes a thermalelectric module 100, and lead frames 220, one or more powersemiconductor chips 140 and 142, one or more control semiconductor chips144 and 146, and a sealing member 160. The power device package 10 mayfurther include a heat sink 170 attached to the second surface 114 ofthe thermal electric module 100; the heat sink 170 is used to dissipateheat. The main features of the power device package 20 according to thecurrent embodiment are as follows. A wiring pattern 210 is formed on afirst surface of the thermal electric module 100, and the powersemiconductor chips 140 and 142 and/or the control semiconductor chips144 and 146 are mounted on the wiring pattern 210.

FIGS. 6A through 6D are schematic cross-sectional views illustrating amethod of fabricating the power device package 20 of FIG. 5 according toanother embodiment of the present invention.

Referring to FIG. 6A, a thermal electric module 100 having a firstsurface 112 and a second surface 114 opposite each other is prepared orotherwise obtained. The thermal electric module 100 includes a pluralityof n-type impurity elements and a plurality of p-type impurity elementswhich are alternately and electrically connected to each other inseries. An operational principle of the thermal electric module 100 hasbeen described above with reference to FIG. 2 and components of thethermal electric module 100 are the same as those of embodimentsdescribed with reference to FIG. 3A or FIG. 3B. However, the materialsare exemplary and the present invention is not limited thereto.

Next, a wiring pattern 210 is formed on the first surface 112 of thethermal electric module 100. The first surface 112 of the thermalelectric module 100 may comprise a surface of the insulating members 107and 107 a described above with reference to FIGS. 3A and 3B. The wiringpattern 210 may be formed by a typical film deposition method, such aschemical vapor deposition (CVD) or physical vapor deposition (PVD), or aplating method, such as electroplating or electroless plating. Thewiring pattern 210 may include a conductive material such as a metal.For example, the wiring pattern 210 may include aluminum, an aluminumalloy, copper, or a copper alloy, or a combination thereof. The wiringpattern 210 may further include nickel, gold, or an alloy thereof. Inother words, when the wiring pattern 210 is formed of a material withpoor oxidation resistance, such as copper or a copper alloy, the wiringpattern 210 may be coated with a layer including nickel, gold, or analloy thereof to prevent oxidation of the copper or copper alloy.However, the materials of the wiring pattern 210 are exemplary and thepresent invention is not limited thereto.

Referring to FIG. 6B, one or more power semiconductor chips 140 and 142are mounted on the wiring pattern 210. The power semiconductor chips 140and 142 may be attached to the wiring pattern 210 by using a chipadhesive member 130. Also, one or more control semiconductor chips 146may be mounted on the wiring pattern 210, and may be electricallyconnected so as to control one or more of the power semiconductor chips140 and 142. The type and number of the power semiconductor chips 140and 142 and the control semiconductor chips 146 are described above. Thepower semiconductor chips 140 and 142 and/or the control semiconductorchip 146 are electrically connected to the wiring pattern 210. Asdescribed above, the power semiconductor chips 140 and 142 and/or thecontrol semiconductor chips 146 may be electrically connected to thewiring pattern 210 in the form of flip chips, or may be electricallyconnected to the wiring pattern 210 by using wires 150 or solder balls.Wire 150 may include a metal such as aluminum (Al), an aluminum alloy,gold (Au), or a gold alloy.

Referring to FIG. 6C, a lead frame 220 is attached to the wiring pattern210 of the thermal electric module 100 by using a conductive adhesivemember 212 (that is, in general, the lead frame and the thermal electricmodule are assembled together). The conductive adhesive member 212 mayinclude a solder, a solder paste, or an Ag paste, or a combinationthereof. In FIG. 6C, an end portion 220 a of the lead frame 220 iselectrically connected to the wiring pattern 210 by using the conductiveconnecting member 212, the control semiconductor chip 144 is mounted onanother end portion 220 b of the lead frame 220, and the end portion 220b of the lead frame 220 is electrically connected to the wiring pattern210 by using a lead frame wiring 222. As described above, the controlsemiconductor chips 144 may be electrically connected to the lead frame220 in the form of flip chips, or may be electrically connected to thelead frame 220 by using wires 152 or solder balls. Wire 152 may includea metal such as aluminum (Al), an aluminum alloy, gold (Au), or a goldalloy. However, the lead frame 220 is exemplary and the presentinvention is not limited thereto. Alternatively, the lead frame 120 maybe integrally formed with the end portion 220 a and the end portion 220b, or may be separately formed to respectively include the end portion220 a and the end portion 220 b from each other.

Next, the thermal electric module 100 and the lead frame 220 areelectrically connected to each other. That is, the power wiring 109shown in FIG. 3A or FIG. 3B is electrically connected to the lead frame220, so that power can be supplied to the thermal electric module 100through the lead frame 220. In FIG. 4B, the power wiring 109 isconnected to power wiring 109 of the lead frame 220. However, this isexemplary, and alternatively, the power wiring 109 may be connected tothe end portion 220 a of the lead frame 220. An electrical connectionbetween the lead frame 220 and the power wiring 109 can be realizedusing a conventional method such as a soldering method. Although notshown in the drawing, the power wiring 109 may be connected to anexternal circuit without being connected to the lead frame 220, so thatpower can be supplied to the thermal electric module 100.

Referring to FIG. 6D, the power device package 10 is encapsulated byusing a sealing member 160 by performing a typical transfer moldingprocess or a curing process. The type of the sealing member 160 and thesealing process using the sealing member 160 are described above withreference to FIG. 4E. Also, trimming of the lead frame's leads isperformed so that only the external leads 220 c and 220 d are leftexposed to the outside of the sealing member 160 (while other leads aretrimmed), and bending of the external leads 220 c and 220 d isperformed, thereby completing the power device package 20.

Referring back to FIG. 5, the power device package 10 may furtherinclude a heat sink 170 attached to the exposed second surface 114 ofthe thermal electric module 100; the heat sink 170 is used to dissipateheat. The heat sink 170 has been described above with reference to FIG.1.

Power device packages according to the present invention use thermalelectric modules realizing the Peltier effect, which can transfer heatby applying current, instead of using ceramic substrates with poorthermal conductivity, so that heat generated from power semiconductorchips is rapidly dissipated to the outside, thereby increasing operationreliability of the devices.

Moreover, since a power device package according to the presentinvention puts the power semiconductor chips and the controlsemiconductor chips for controlling and driving the power semiconductorchips into one package, smart power modules or intelligent power modulescan be realized.

The foregoing is illustrative of example embodiments and is not to beconstrued as limiting thereof. Although example embodiments have beendescribed, those skilled in the art will readily appreciate that manymodifications are possible in example embodiments without materiallydeparting from the novel teachings and advantages of exampleembodiments. Accordingly, all such modifications are intended to beincluded within the scope of the claims. Therefore, it is to beunderstood that the foregoing is illustrative of example embodiments andis not to be construed as limited to the specific embodiments disclosed,and that modifications to the disclosed embodiments, as well as otherembodiments, are intended to be included within the scope of theappended claims. Example embodiments are defined by the followingclaims, with equivalents of the claims to be included therein.

1. A power device package comprising: a thermal electric module having afirst surface and a second surface opposite each other, and a pluralityof n-type impurity elements and a plurality of p-type impurity elementsalternately and electrically connected to each other in series; a leadframe attached to the first surface of the thermal electric module by anadhesive member; one or more power semiconductor chips disposed on andelectrically connected to the lead frame; one or more controlsemiconductor chips disposed on and electrically connected to the leadframe to control at least one power semiconductor chip; and a sealingmember sealing the thermal electric module, the one or more powersemiconductor chips, the one or more control semiconductor chips, and atleast a portion of the lead frame so as to expose the second surface ofthe thermal electric module.
 2. The power device package of claim 1,wherein the thermal electric module comprises: an impurity element arrayportion having the n-type impurity elements and the p-type impurityelements arranged in an alternating manner; a first plurality ofconductive members disposed on the impurity element array portion and asecond plurality of conductive members disposed below the impurityelement array portion, the conductive members electrically connectingthe n-type impurity elements and the p-type impurity elements in series;a power wiring electrically connected to a portion of the conductivemembers and adapted to convey electrical power to the impurity elementarray portion from the outside; and a first insulating member disposedon at least a portion of the first conductive members, and a secondinsulating member disposed below at least a portion of the secondconductive members.
 3. The power device package of claim 2, wherein theimpurity element array portion comprises a semiconductor substrate,wherein the n-type impurity elements comprise n-type impurity regions inthe semiconductor substrate, the n-type regions having n-type doped orion-implanted impurities disposed in the semiconductor substrate, andwherein the p-type impurity elements comprise p-type impurity regions inthe semiconductor substrate, the p-type regions having p-type doped orion-implanted impurities disposed in the semiconductor substrate.
 4. Thepower device package of claim 2, wherein the conductive members comprisealuminum, an aluminum alloy, copper, a copper alloy, nickel, a nickelalloy, or a combination thereof.
 5. The power device package of claim 2,wherein the power wiring is electrically connected to the lead frame andadapted to convey electrical power to the impurity element arrayportion.
 6. The power device package of claim 1, wherein the n-typeimpurities included in the n-type impurity elements comprise one or moreselected from the group consisting of N, P, As, Sb, Bi, S, Se, Te, andPo, and the p-type impurities comprised in the p-type impurity elementscomprise one or more selected from the group consisting of B, Al, Ga,In, Tl, Zn, Cd, and Hg.
 7. The power device package of claim 1, whereinat least one semiconductor chip is disposed so as to be electricallyconnected to the lead frame in the form of a flip chip or iselectrically connected to the lead frame with at least one wire or atleast one solder ball, wherein the at least one semiconductor chip is apower semiconductor chip or a control semiconductor chip.
 8. The powerdevice package of claim 7, wherein the at least one wire comprisesaluminum or gold.
 9. The power device package of claim 1, wherein theone or more power semiconductor chips comprise one or more power metaloxide semiconductor field effect transistors, one or more bipolarjunction transistors, one or more insulated-gate bipolar transistors, orone or more diodes, or a combination thereof.
 10. The power devicepackage of claim 1, wherein the sealing member comprises an epoxymolding compound, a polyimide, a silicone, a silicone rubber, or acombination thereof.
 11. The power device package of claim 1, furthercomprising a heat sink attached to the second surface of the thermalelectric module.
 12. The power device package of claim 11, wherein theheat sink comprises aluminum, an aluminum alloy, copper, a copper alloy,an aluminum oxide, a beryllium oxide, an aluminum nitride, a siliconnitride, or an epoxy-based resin, or a combination thereof.
 13. Thepower device package of claim 1, wherein the lead frame adhesive membercomprises an elastomer or an epoxy, or a combination thereof.
 14. Apower device package comprising: a thermal electric module having afirst surface and a second surface opposite each other, and a pluralityof n-type impurity elements and a plurality of p-type impurity elementsalternately and electrically connected to each other in series; a wiringpattern disposed on the first surface; a lead frame attached to thefirst surface of the thermal electric module by a conductive adhesivemember and electrically connected to the wiring pattern; one or morepower semiconductor chips disposed on and electrically connected to thewiring pattern; one or more control semiconductor chips disposed on andelectrically connected to the lead frame or the wiring pattern, or both,to control the at least one power semiconductor chip; and a sealingmember sealing the thermal electric module, the one or more powersemiconductor chips, the one or more control semiconductor chips, and atleast a portion of the lead frame so as to expose the second surface ofthe thermal electric module.
 15. The power device package of claim 14,wherein the thermal electric module comprises: an impurity element arrayportion having the n-type impurity elements and the p-type impurityelements arranged in an alternating manner; a first plurality ofconductive members disposed on the impurity element array portion and asecond plurality of conductive members disposed below the impurityelement array portion, the conductive members electrically connectingthe n-type impurity elements and the p-type impurity elements in series;a power wiring electrically connected to a portion of the conductivemembers and adapted convey electrical power to the impurity elementarray portion from the outside; and a first insulating member disposedon at least a portion of the first conductive members, and a secondinsulating member disposed below at least a portion of the secondconductive members.
 16. The power device package of claim 15, whereinthe impurity element array portion comprises a semiconductor substrate,wherein the n-type impurity elements comprise n-type impurity regions inthe semiconductor substrate, the n-type regions having n-type doped orion-implanted impurities disposed in the semiconductor substrate, andwherein the p-type impurity elements comprise p-type impurity regions inthe semiconductor substrate, the p-type regions having p-type doped orion-implanted impurities disposed in the semiconductor substrate. 17.The power device package of claim 15, wherein the power wiring iselectrically connected to the lead frame and adapted to conveyelectrical power to the impurity element array portion.
 18. The powerdevice package of claim 14, wherein the wiring pattern comprisesaluminum, an aluminum alloy, copper, or a copper alloy, or a combinationthereof.
 19. The power device package of claim 18, wherein the wiringpattern further comprises nickel, gold, or an alloy thereof.
 20. Thepower device package of claim 14, wherein the conductive adhesive membercomprises a solder, a solder paste, or a silver paste, or a combinationthereof.
 21. The power device package of claim 14, wherein at least onesemiconductor chip is disposed so as to be electrically connected to thelead frame in the form of a flip chip or is electrically connected tothe lead frame with at least one wire or at least one solder ball,wherein the at least one semiconductor chip is a power semiconductorchip or a control semiconductor chip.
 22. The power device package ofclaim 21, wherein the at least one wire comprises aluminum or gold. 23.The power device package of claim 14, further comprising a heat sinkattached to the second surface of the thermal electric module.
 24. Thepower device package of claim 23, wherein the heat sink comprisesaluminum, an aluminum alloy, copper, a copper alloy, an aluminum oxide,a beryllium oxide, an aluminum nitride, a silicon nitride, or anepoxy-based resin, or a combination thereof.
 25. A method of fabricatinga power device package, the method comprising: assembling a lead frameand a first surface of a thermal electric module together using anadhesive member, the thermal electric module having a second surfaceopposite to the first surface, a plurality of n-type impurity elements,and a plurality of p-type impurity elements, the n-type impurityelements and the p-type impurity elements being alternately andelectrically connected to each other in series; mounting one or morepower semiconductor chips and one or more control semiconductor chips onthe lead frame; electrically connecting at least one power semiconductorchip and at least one control semiconductor chip to the lead frame; andsealing the thermal electric module, the one or more power semiconductorchips, the one or more control semiconductor chips, and a portion of thelead frame with a sealing member so as to expose the second surface ofthe thermal electric module.
 26. The method of claim 25, whereinassembling the lead frame and the thermal electric module togethercomprises electrically connecting the thermal electric module and thelead frame.
 27. The method of claim 25, after the sealing of thesubstrate, the power semiconductor chips, and the portion of the leadframe, the method further comprising: trimming the leads of the leadframe to leave only some of the leads exposed to the outside of thesealing member; and bending the exposed leads.
 28. A method offabricating a power device package, the method comprising: forming awiring pattern on a first surface of a thermal electric module, thethermal electric module having a second surface opposite to the firstsurface, a plurality of n-type impurity elements, and a plurality ofp-type impurity elements, the n-type impurity elements and the p-typeimpurity elements being alternately and electrically connected to eachother in series; mounting one or more power semiconductor chips on thethermal electric module so as to electrically connect to the wiringpattern; assembling a lead frame and the first surface of the thermalelectric module together using a conductive adhesive member so that thelead frame and the wiring pattern are electrically connected; andsealing the thermal electric module, the power semiconductor chips, thecontrol semiconductor chips and a portion of the lead frame with asealing member so as to expose the second surface of the thermalelectric module.
 29. The method of claim 28, wherein the mounting of thepower semiconductor chips on the thermal electric module furthercomprises mounting one or more control semiconductor chips on the wiringpattern so as to be electrically connected to the wiring pattern. 30.The method of claim 28, wherein assembling the lead frame and the firstsurface of the thermal electric module together comprises electricallyconnecting the thermal electric module and the lead frame.